Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

The authors would like to thank the financial support by Deutsche Forschungsgemeinschaft (German Research Foundation) with Project-ID SFB1461 and by the Federal Ministry of Education and Research of Germany under grant numbers 16ES1002, 16FMD01K, 16FMD02 and 16FMD03. The authors also gratefully acknowledge the support of the Spanish Ministry of Science, Innovation and Universities and the FEDER program through project TEC2017-84321-C4-3-R and project A.TIC.117.UGR18 funded by the government of Andalusia (Spain) and the FEDER program. The publication of this article was funded by the Open Access Fund of the Leibniz Association.The datasets generated during and/or analysed during the current study are available from the corresponding author on reasonable request.In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study.German Research Foundation (DFG) SFB1461Federal Ministry of Education & Research (BMBF) 16ES1002 16FMD01K 16FMD02 16FMD03Spanish Ministry of Science, Innovation and UniversitiesEuropean Commission TEC2017-84321-C4-3-Rgovernment of Andalusia (Spain) A.TIC.117.UGR18Leibniz Associatio

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters

Toward Reliable Compact Modeling of Multilevel 1T-1R RRAM Devices for Neuromorphic Systems

In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study